1. Field of the Invention
The present invention relates to a sensing circuit for programming/reading multilevel flash memory, and more particularly, to an improved sensing circuit for programming/reading multilevel flash memory wherein a simplified sense amplifier is employed to maximize the number of sense amplifiers so as to process a plurality of bit data in sequentially processed respective cells in a simplified manner by increasing cell number being processed at one time, thereby enabling a low current operation.
2. Description of the Background Art
A method for programming a multilevel flash memory varies to an iterative program verify technique wherein program and verify are iterated and to an automatic verifying program technique (or simultaneously programming and verifying) wherein all the program requirements are eliminated at the moment of programming while continuously applying a long program pulse until it is completely programmed.
According to the automatic verifying program technique, a cell current variation is detected to determine whether a cell is programmed to a desired extent.
Meanwhile, with regard to a read method of a multilevel flash memory, a sense amplifier having a plurality (level number--1) of comparison circuits are employed to distinguish between respective levers. For example, in order to sense 2 levels (1 bit), a sense amplifier having one comparison circuit is used to sequentially sense while changing the voltage of a control gate.
Here, the program and read should be implemented by identical sense amplifier to maximize the compensation of such as offset in the processing between respective transistors so that it is possible to minimize a cell threshold voltage distribution between respective sense amplifiers.
FIG. 1 is a circuit view illustrating a first example of a sensing circuit for programming/reading a multilevel flash memory according to the conventional art to implement a 4-level sensing. As shown therein, the circuit includes a PMOS transistor PM1 with its source connected to a supply voltage VDD and its gate and drain connected in common so as to be connected to the drain of a selected cell, a reference voltage generator 5 for generating first to third reference voltages VREF1-VREF3, a first to third comparators 1-3 with their each one terminal connected to the drain of the selected cell FMC and the other terminals thereof applied by the first to third reference terminals VREF1-VREF3 for thereby outputting compared results X1-X3, and a decoding unit 4 for decoding the outputs X1-X3 of the first to third comparators 1-3 and outputting 2-bit data MSB, LSB.
The operation of the first example of the sensing circuit for programming/reading the conventional multilevel flash memory will now be described.
As shown in FIG. 2, when a predetermined voltage VG is applied to the control gate of a flash memory cell having a four-threshold voltage distribution, the current ICELL in the cell is also represented in four-current value distributions ICELL1-ICELL4 as shown in FIG. 3. Such current values are converted to voltage and concurrently compared to three reference voltages VREF1-VREF3 using the first to third comparators 1-3. The compared result is decoded by the decoding unit 4 and the information as to where to exist among the four levels is converted to 2-bit data MSB, LSB.
FIG. 4 is a circuit view illustrating a second example of a sensing circuit for programming/reading a conventional multilevel flash memory, wherein four levels are sensed. As shown therein, the circuit includes a PMOS transistor PM11 with its source connected to a supply voltage VDD and its gate and drain connected in common so as to be connected to the drain of a selected cell, a reference voltage generator 13 for generating a reference voltage VREF, a comparator 11 with its one terminal connected to the drain of the selected cell FMC and the other terminal applied by the reference voltage VREF, and a decoding unit 12 for decoding the output of the comparator 11 and outputting 2-bit data MSB, LSB.
The operation of the second example of the sensing circuit for programming/reading the conventional multilevel flash memory will now be described.
As shown in FIG. 5, the intermediate voltage values of the four threshold voltage distributions are sequentially applied to the control gate of the flash memory cell through three steps while increasing or decreasing so that each step determines whether there is a current that runs to the cell by the comparator 11 and detects the moment of current running. Therefore, as shown in FIG. 6, the decoding unit 12 receives the output of the comparator 11 with regard to the information as to where it locates among the four levels and it is converted to 2-bit data MSB, LSB.
FIG. 7 is a circuit view illustrating a third example of the sensing circuit for programming/reading a conventional multilevel flash memory, wherein four levels are sensed. As shown therein, the circuit includes a PMOS transistor PM21 with its source connected to a supply voltage VDD and its gate and drain connected in common so as to be connected to the drain of a selected cell, a comparator 21 with its one terminal connected to the drain of the selected cell and the other terminal applied by a second reference voltage IREF2 and a second comparator 22 with the other terminal applied to a first reference current IREF1 or a third reference current IREF3, a first reference current generator for generating the second reference current IREF2, a second reference current generator 24 for receiving the output X1 of the first comparator 21 and selectively generating the first reference current IREF1 or the third reference current IREF3, and a decoding unit 25 for decoding the outputs X1, X2 of the first and second comparators 21, 22 and outputting 2-bit data MSB, LSB.
The operation of the third example of the sensing circuit for programming/reading the conventional multilevel flash memory will now be described.
As shown in FIG. 8,the cell current ICELL is compared to the second reference current IREF2 so as to determine the upper two or lower two of the four threshold voltage distributions and MSB is determined. The cell current ICELL and the second reference current IREF2 are compared and according to the compared result X1, the second reference current generator 24 selectively outputs the first current IREF1 or the third current IREF3. The first reference current IREF1 or the third reference current IREF3 selectively outputted by the cell current ICELL and the second reference current generator 24 is compared in the second comparator 22 to determined the most significant bit LSB.
Likewise, the conventional sensing circuit for programming/reading a multilevel flash memory employs repetition of programming and verifying, so that the lower the threshold voltage of the cell during the sensing, the more current flows, thereby increasing memory consumption and circuit size.